AT697F datasheet(29/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Figure 12. RAM read access with one programmed waitstate

data2

waitstate

lead-out

CLK

RAMS*

OE*

data1

For and only for RAM bank 4, If the application needs more delay during the SRAM transfer, it is

possible to introduce more delay by activating the hardware bus ready ( BRDY* ) detection in

MCFG2. Refer to paragraph “BRDY Wait states”, page 38.

Bus width

To support applications with low memory performance requirements, the SRAM area can be

configured for 8-bit operations. The configuration of SRAM in 8-bit mode is done programming

MCFG2 RAMWDH, SRAM bus width field.

When the SRAM bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as

interface.

Figure 13.

SRAM

RAMOE0*

AT697F

A[27:0]

D[31:24]

A[27:0]

RWE0*

RAMS0*

SRAM 8-bit bus width connection

Since access to memory is always done on 32-bit word basis, read access to 8-bit memory will

be transformed in a burst of four read transactions. If EDAC protection is active, 5 read cycles

are necessary to complete the access (please refer to “Error Management - EDAC”, page 40 for

more details). During write operation, only the necessary bytes are writen.

AT697F 数据表(PDF) 29 Page - ATMEL Corporation