AT697F datasheet(49/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

General

Purpose

Interface

The general purpose interface (GPI) consists in a 32-bit wide I/O port with alternate facilities.

GPI as 32-bit I/O

port

The interface is based on bi-directional I/O ports.The port is split in two parts, with the lower 16-

bits accessible by the parallel IO pads and the upper 16-bits via the data bus.

lower 16-bits

The lower 16-bits of the general purpose interface are accessible through PIO[15:0]. All I/O ports

have true Read-Modify-Write functionality when used as general I/O ports. This means that the

direction of one port pin can be changed without unintentionally the direction of any other pin.

The same applies when changing the drive value of the port.

Figure 33. I/O port block diagram

IO Direction Reg.

IO Data Reg.

IODIR

IODAT

PIOx

clock

- PIO[15:0]

configuring the pin

Each pin from PIO[15:0] consists of two register bits : IODIRx and IODATx. As shown in the

“Register Description” section, the IODIRx bits are accessed at IODIR address and iodatx at

IODAT address.

The IODIR IODIRx bit selects the direction for port number x. If IODIRx is written logic one, the

corresponding pin is configured as output. If written logic zero, the pin is configured as an input.

When the pin is configured as an input, a read of the IODAT IODATx bit returns the current

value of the pin. When the pin is configured as an output, if a logical one is written to IODAT-

IODATx bit, the port x is driven high. If a logical zero is written to IODAT IODATx bit, the port

x is driven low.

switching between input

& output

When the port x is switched from input to output by switching IODIRx, the value of IODATx is

immediatly driven on the corresponding pin.When switched from output to input by toggling

IODIRx, the value from the pin is immediatly written to IODATx.

upper 16-bits

The upper 16-bits of the general purpose interface are accessible through D[15:0]. They can

only be used when all memory areas (ROM, RAM and I/O) are 8-bit wide. If the SDRAM control-

ler is enabled, the upper 16-bits cannot be used.

Figure 34. I/O port block diagram

IO Direction Reg.

IO Data Reg.

MEDDIR/LOWDIR

MEDDAT/LOWDAT

clock

- D[15:0]

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