AT697F datasheet(45/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

If a tag parity error is detected during a cache access, a cache miss is generated. The tag and

the data are automatically updated. All valid bits except the one corresponding to the newly

loaded data are cleared. Each error is reported in the instruction cache tag error counter from

the CCR. The instruction cache tag error counter CCR ITE is incremented after each instruc-

tion cache tag error detection.

If a data sub-block parity error occurs, a miss is also generated but only the failed sub-block is

updated with data from main memory. Each error is reported in the instruction cache data error

counter from the CCR. The instruction cache data error counter CCR IDE is incremented after

each instruction cache data error detection.

Data Cache

Overview

The AT697F data cache is a multi-set cache of 16 kbyte divided in 2 memory sets. Multi-set-

cache use improves speed performance. The data cache is divided into cache lines with 16

bytes of data. Each line has a cache tag associated with it consisting of a tag field and one valid

bit per 4-byte sub-block.

Cache Control

The instruction cache operations are controled with the cache control register (CCR).

Operation

Write

The write policy for stores is write-through with no-allocate on write-miss. The write buffer (WRB)

consists of three 32-bit registers used to temporarily hold store data until it is sent to the destina-

tion device. For half-word or byte stores, the stored data replicated into proper byte alignment for

writing to a word-addressed device, before being loaded into one of the WRB registers.

The WRB is emptied prior to a load-miss cache-fill sequence to avoid any stale data from being

read in to the data cache.

Read

On a data cache read-miss to a cachable location, 4 bytes of data are loaded into the cache

from main memory.

Cache Flush

Data cache can be flushed by executing the FLUSH instruction, setting logical one in CCR FD

in the cache control register, or writing any location with ASI=0x6. The flush operation takes one

cycle per line during which the IU will is not halted, but during which the cache is disabled. When

the flush operation is completed, the cache will resume the state indicated in the cache control

Error Reporting

Since the processor executes in parallel with the write buffer, a write error will not cause an

exception to the store instruction. Depending on memory and cache activity, the write transac-

tion may not occur until several clock cycles after the store instructions has completed. If a write

error occurs, the currently executing instruction will take trap 0x2B.

Note:

the 0x2B trap handler should flush the data cache, since a write hit would update the cache while

the memory would keep the old value due the write error.

If a memory access error occurs during a data load, the corresponding valid bit in the cache tag

will not be set. and a data access error trap (tt=0x09) is generated.

Data Cache Parity

Error detection of cache tags and data is implemented using two parity bits per tag and per 4-

byte data sub-block. The tag parity is generated from the tag value and the valid bits. The data

parity is derived from the sub-block data. The parity bits are written simultaneously with the

associated tag or sub-block and checked on each access. The two parity bits correspond to the

parity of odd and even data (tag) bits.

If a tag parity error is detected during a cache access, a cache miss is generated. The tag and

the data are automatically updated. All valid bits except the one corresponding to the newly

loaded data are cleared. Each error is reported in the instruction cache tag error counter from

the CCR. CCR DTE is incremented after each data cache tag error detection.

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