ADIS16220

Rev. 0 | Page 8 of 20

THEORY OF OPERATION

The ADIS16220 is a wide-bandwidth, digital acceleration sensor

for vibration analysis. This sensing system collects data

autonomously and makes it available to any processor system

that supports a 4-wire serial peripheral interface (SPI).

SENSING ELEMENT

Digital vibration sensing in the ADIS16220 starts with a wide-

bandwidth MEMS accelerometer core that provides a linear

motion-to-electrical transducer function. Figure 6 provides a

basic physical diagram of the sensing element and its response

to linear acceleration. It uses a fixed frame and a moving frame

to form a differential capacitance network that responds to

linear acceleration. Tiny springs tether the moving frame to the

fixed frame and govern the relationship between acceleration

and physical displacement. A modulation signal on the moving

plate feeds through each capacitive path into the fixed frame

plates and into a demodulation circuit, which produces the

electrical signal that is proportional to the acceleration acting on

the device.

MOVABLE

FRAME

UNIT

FORCING

CELL

UNIT SENSING

CELL

MOVING

PLATE

FIXED

PLATES

PLATE

CAPACITORS

ANCHOR

ANCHOR

Figure 6. MEMS Sensor Diagram

DATA SAMPLING AND PROCESSING

The analog acceleration signal feeds into an analog-to-digital

(ADC) converter stage, which passes digitized data into the

controller. The controller processes the acceleration data, stores

it in the capture buffer, and manages access to it using the

SPI/register user interface. Processing options include offset

adjustment, filtering, and checking for preset alarm conditions.

MEMS

SENSOR

CLOCK

CONTROLLER

CAPTURE

BUFFER

CONTROL

REGISTERS

OUTPUT

REGISTERS

TEMP

SENSOR

AIN

SIGNALS

ADC

Figure 7. Simplified Sensor Signal Processing Diagram

USER INTERFACE

SPI Interface

The user registers control operation and manage user access to

both sensor data and configuration inputs. Each 16-bit register

has its own unique bit assignment and has two addresses: one for

its upper byte and one for its lower byte. Table 8 provides a

memory map for each register, along with their function and

lower byte address. Each data collection and configuration

commands both use the SPI, which consists of four wires. The

chip select (CS) signal activates the SPI interface and the serial

clock (SCLK) synchronizes the serial data lines. Input commands

clock into the DIN pin, one bit at a time, on the SCLK rising

edge, and output data clocks out of the DOUT pin on the SCLK

falling edge. As a SPI slave device, the DOUT contents reflect

the information requested using a DIN command.

Dual Memory Structure

The user registers provide addressing for all input/output opera-

tions on the SPI interface. The control registers use a dual memory

structure. The SRAM controls operation while the part is on, and

facilitates all user configuration inputs. The flash memory pro-

vides nonvolatile storage for control registers that have flash

backup (see Table 8). Storing configuration data in the flash

memory requires a manual, flash update command (GLOB_

CMD[12] = 1, DIN = 0xBF10). When the device powers on or

resets, the flash memory contents load into the SRAM, and then

the device starts producing data according to the configuration

in the control registers.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 8. SRAM and Flash Memory Diagram