ADIS16220

Rev. 0 | Page 9 of 20

BASIC OPERATION

The ADIS16220 uses a serial peripheral interface (SPI) for

communication, which enables a simple connection with a

compatible, embedded processor platform, as shown in Figure

9.

The two general-purpose lines provide options for a busy indica-

tor, an alarm indicator, a general-purpose input/output function,

and an external capture trigger input.

CS

ADIS16220

SPI SLAVE

SCLK

DIN

DOUT

DIO1

DIO2

SS

VDD

SYSTEM PROCESSOR

SPI MASTER

SCLK

MOSI

MISO

IRQ1

IRQ2

6

5

2

3

1

4

13

16

Figure 9. Electrical Hook-Up Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

IRQ1, IRQ2

Interrupt request inputs

MOSI

Master output, slave input

MISO

Master input, slave output

SCLK

Serial clock

The ADIS16220 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 13. Table 7 provides a list of

the most common settings that require attention to initialize a

processor’s serial port for the ADIS16220 SPI interface.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16220 operates as a slave

SCLK Rate ≤ 2.25 MHz

Bit rate setting

SPI Mode 3 (1, 1)

Clock polarity/phase (CPOL = 1, CPHA = 1)

MSB-First

Bit sequence

16-Bit

Shift register/data length

The user registers in Table 8 govern all data collection and

configuration. Figure 10 provides a generic bit assignment when

referencing each registers’ bit descriptions.

UPPER BYTE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LOWER BYTE

Figure 10. Generic Register Bit Definitions

SPI WRITE COMMANDS

The control registers in Table 8 provide configuration options for

a variety of functions. A master processor writes to the registers,

one byte at a time, using simple firmware commands and the bit

assignments in Figure 13. Because each byte in a register is

independent, some functions only require one write cycle. For

example, set GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a

manual capture sequence. The manual capture starts imme-

CS

DIN

SCLK

Figure 11. SPI Sequence for Manual Capture Start (DIN = 0xBF08)

SPI READ COMMANDS

A single register read requires two 16-bit SPI cycles, which also

use the bit assignments in Figure 13. The first sequence sets

R/W = 0 and communicates the target address (A6:A0). For a

read request, D7:D0 are don’t care bits. For simplicity, set D7:D0

equal to zero during read request commands. DOUT clocks out

during the second sequence. The second sequence can also use

DIN to setup the next read. Figure 12 provides a signal diagram

for all four SPI signals while reading the acceleration capture

buffer (CAPT_BUFA) in a repeating pattern. In this diagram,

DIN = 0x1400 and DOUT reflects the CAPT_BUFA register

contents.

DOUT = 1111 1001 1101 1010 = 0xF9DA = –1573 LSBs

≥ –30.002g

DIN = 0001 0100 0000 0000 = 0x1400

SCLK

CS

DIN

DOUT

Figure 12. Example SPI Read, Second 16-Bit Sequence

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

NOTES

1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).

CS

SCLK

DIN

DOUT

A6

A5

DB13

DB14

DB15

Figure 13. Example SPI Read Sequence