ADIS16220

Rev. 0 | Page 15 of 20

Table 29. DIAG_STAT Bit Descriptions

Bit

Description (Default = 0x0000)

[15]

Reserved

[14]

AIN2 sample > ALM_MAG2

[13]

AIN1 sample > ALM_MAG1

[12]

Acceleration sample > ALM_MAGA

[11]

Error condition programmed into ALM_MAGS[11:0] and

ALM_CTRL[5:4] is true

[10]

|Peak value in AIN2 data capture| > ALM_MAG2

[9]

|Peak value in AIN1 data capture| > ALM_MAG1

[8]

|Peak value in acceleration data capture| > ALM_MAGA

[7]

Data ready, capture complete

[6]

Flash test result, checksum flag

[5]

Self-test diagnostic error flag

[4]

Capture period violation/interruption

[3]

SPI communications failure

[2]

Flash update failure

[1]

Power supply above 3.625 V

[0]

Power supply below 3.15 V

Self-Test

The internal MEMS sensing element has an electrostatic self-

test function that simulates the physical displacement associated

with an acceleration event. There are two options for using this

feature to verify the integrity of the accelerometer sensor and signal

chain. Set GLOB_CMD[2] = 1 to execute an automatic self-test

sequence, which exercises the sensing element, observes the

change in output, records it into ST_DELTA, compares it with pre-

set minimum/maximum values, and reports the pass/fail result in

DIAG_STAT[5].

Another option is to set MSC_CTRL[8] = 1 (see Table 30) to

manually activate the sensing element. Then execute a manual

capture, which reflects the response associated with the self-test

setting.

Table 30. MSC_CTRL Bit Descriptions

Bit

Description (Default = 0x0003)

[15:9]

Reserved

[8]

Self-test enable, set to 1 to activate,

(returns to 0 when complete)

[7:2]

Reserved

[1]

Power supply compensation, AIN2

1 = enable, 0 = disable

[0]

Power supply compensation, AIN1

1 = enable, 0 = disable

MSC_CTRL[1:0] provides an option for reducing the sensitivity

dependence on power supply for ratiometric sensors, such as

the ADXL001.

Table 31. ST_DELTA Bit Descriptions

Bit

Description

[15:0]

Acceleration data, twos complement, 19.073 mg/LSB

SERIALIZATION

LOT_ID1 and LOT_ID2 combine to provide a unique lot code

that is 24 bits in length. SERIAL_NUM provides a unique serial

number for each device within a given lot.

Table 32. LOT_ID1 Bit Descriptions

Bit

Description

[15:8]

Lot identification code, least significant byte

[7:0]

Reserved for internal use, do not use

Table 33. LOT_ID2 Bit Descriptions

Bit

Description

[15:0]

Lot identification code, most significant bytes

Table 34. SERIAL_NUM Bit Descriptions

Bit

Description

[15:0]

Serial number, lot-specific

FLASH MEMORY MANAGEMENT

The FLASH_CNT register (see Table 35) provides a tool for

managing the flash memory’s endurance. The FLASH_CNT

register increments every time there is a write to the flash

memory. Figure 16 quantifies the relationship between data

retention and junction temperature.

Table 35. FLASH_CNT Bit Descriptions

Bit

Description

[15:0]

Binary counter for writing to flash memory

600

450

300

150

0

30

40

JUNCTION TEMPERATURE (°C)

55

70

85

100

125

135

150

Figure 16. Flash/EE Memory Data Retention