ADRF6602ACPZ-R7 datasheet(4/24 Pages) AD

4 / 24 page

ADRF6602

Rev. 0 | Page 4 of 24

SYNTHESIZER/PLL SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized

using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNTHESIZER SPECIFICATIONS

Synthesizer specifications referenced to 1× LO

Frequency Range

Internally generated LO

1550

2150

MHz

Figure of Merit

PREF_IN = 0 dBm

−222

dBc/Hz

Reference Spurs

fREF = 153.6 MHz

fREF/4

−105

dBc

fREF/2

−105

dBc

fREF

−80

dBc

> fREF

−85

dBc

PHASE NOISE

fLO = 1550 MHz to 2150 MHz, fPFD = 38.4 MHz

1 kHz to 10 kHz offset

−90

dBc/Hz

100 kHz offset

−103

dBc/Hz

500 kHz offset

−122

dBc/Hz

1 MHz offset

−130

dBc/Hz

5 MHz offset

−142

dBc/Hz

10 MHz offset

−148

dBc/Hz

20 MHz offset

−150

dBc/Hz

Integrated Phase Noise

1 kHz to 40 MHz integration bandwidth

0.3

°rms

PFD Frequency

MHz

REFERENCE CHARACTERISTICS

REF_IN, MUXOUT pins

REF_IN Input Frequency

160

MHz

REF_IN Input Capacitance

MUXOUT Output Level

VOL (lock detect output selected)

0.25

VOH (lock detect output selected)

2.7

MUXOUT Duty Cycle

CHARGE PUMP

Pump Current

Programmable to 250 μA, 500 μA, 750 μA, 1 mA

500

μA

Output Compliance Range

2.8

ADRF6602ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

ADRF6602ACPZ-R7 数据表(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载

链接网址

ADRF6602ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

ADRF6602ACPZ-R7 数据表(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表 下载

链接网址

数据表下载