ADRF6602

Rev. 0 | Page 5 of 24

LOGIC INPUT AND POWER SPECIFICATIONS

using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

CLK, DATA, LE

1.4

3.3

V

0

0.7

V

0.1

μA

5

pF

POWER SUPPLIES

VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range

4.75

5

5.25

V

Supply Current

PLL only

97

mA

External LO mode (internal PLL disabled,

IP3SET pin = 3.3 V)

165

mA

Internal LO mode (internal PLL enabled,

IP3SET pin = 3.3 V)

262

mA

Power-down mode

30

mA

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 4.

Parameter

Limit

Unit

Description

20

ns min

LE setup time

10

ns min

DATA to CLK setup time

10

ns min

DATA to CLK hold time

25

ns min

CLK high duration

25

ns min

CLK low duration

10

ns min

CLK to LE setup time

20

ns min

LE pulse width

Timing Diagram

CLK

DATA

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

Figure 2. Timing Diagram