ADRF6602

Rev. 0 | Page 14 of 24

RESERVED

REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5)

RES

PLL

EN

LO

DIV1

LO

EXT

LO

DRV

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7

0

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CD3

CD2 CD1 CD0

PLEN

LDV1

LXL

LDRV C3(1) C2(0) C1(1)

LDRV

0

1

LXL

0

1

LDV1

0

1

DIVIDE BY 1

DIVIDE BY 2 (DEFAULT)

LO OUTPUT DRIVER

ENABLE

DRIVER OFF (DEFAULT)

DRIVER ON

PLEN

0

1

DISABLE

ENABLE (DEFAULT)

PLL ENABLE

EXTERNAL LO DRIVE

ENABLE (PIN 37, PIN 38)

INTERNAL LO OUTPUT (DEFAULT)

EXTERNAL LO INPUT

DIVIDE-BY-2 IN LO CHAIN ENABLE

CAP DAC

CONTROL BITS

CD3

CD2

CD1

CD0

00

00

11

11

MIN

MAX

CAPACITOR DAC

CONTROL FOR IIP3

OPTIMIZATION

00

0

0

0

000

000

0

VCO EN

VCO ENABLE

DISABLE

ENABLE (DEFAULT)

Figure 18. Register 5—PLL Enable and LO Path Control Register Map

REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106)

CHARGE

PUMP

ENABLE

3.3V

LDO

ENABLE

VCO

ENABLE

VCO

SWITCH

VCO

BW SW

CTRL

VBSRC

0

1

VCO LDO

ENABLE

VCO AMPLITUDE

RESERVED

VCO BAND SELECT FROM SPI

VBS[5:0]

VCO BAND SELECT FROM SPI

0x00

DEFAULT 0x20

CHARGE PUMP ENABLE

0x01

….

0x00

0

….

….

0x18

24 (DEFAULT)

….

….

0x2B

43 (RECOMMENDED)

….

….

0x3F

63

0x3F

VCO BW CAL AND SW SOURCE CONTROL

BAND CAL (DEFAULT)

VCO SW

0

1

VCO SWITCH CONTROL FROM SPI

REGULAR (DEFAULT)

BAND CAL

SPI

DB22 DB21

DB20

DB19

DB18

DB17

DB16

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5 DB4

DB3 DB2 DB1

DB0

CONTROL BITS

DB23

CPEN

L3EN

VCO EN VCO SW

VC5

VC4

VC3

VC2

VC1

VC0

VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)

LVEN

VC[5:0]

VCO AMPLITUDE

0

1

LVEN

VCO LDO ENABLE

DISABLE

0

ENABLE (DEFAULT)

1

L3EN 3.3V LDO ENABLE

DISABLE

ENABLE (DEFAULT)

0

1

CPEN

DISABLE

ENABLE (DEFAULT)

0

1

000

Figure 19. Register 6—VCO Control and VCO Enable Register Map

REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007)

DB23

DB22

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3 DB2 DB1

DB0

0XVCO

XVCO

RES

MBE

0

0

0

0

0

0

0

000

0

000

0

0

0

0

C3(1) C2(1) C1(1)

MIXER

B_EN

RESERVED

CONTROL BITS

MBE

0

1

MIXER BIAS ENABLE

DISABLE

ENABLE (DEFAULT)

XVCO

0

1

INTERNAL VCO (DEFAULT)

EXTERNAL VCO

EXTERNAL VCO

Figure 20. Register 7—Mixer Bias Enable and External VCO Enable Register Map