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AS8530

Preliminary Data Sheet - D e t a i l e d D e s c r i p t i o n

Figure 4. Reset Functionality

The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of

RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initializes Window

under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.

7.1.6 Window Watchdog (WWD)

To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated

function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions,

microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or

occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit

enabled, there is a 3-bit factory programming available to set the trigger window.

Figure 5. Window Watchdog Trigger

VCC

VSUP

VUVR_OF

F

T>Tj

T<Tj

RESET

Initialisation

Thermal shutdown

Spike VSUP

Low voltage VSUP

Current limitation active

VUVR_ON

MISSING

WATCHDOG

ACCESS

Period

Non-Service time (W D_TCL)

Service time (W D_TSV)

Trigger

restart

period

Trigger via

SPI

Last trigger point

Earliest possible

trigger point

(System will not

RESET)

latest possible

trigger point

(System wil not be

RESET)

50 %

100 %

Valid Trigger point

(System will not be

RESET)

Unwanted trigger point

(System will be

RESET)