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AS8530-ASOT 数据表(PDF) 21 Page - ams AG |
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AS8530-ASOT 数据表(HTML) 21 Page - ams AG |
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21 / 29 page ![]() www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 0.01 21 - 29 AS8530 Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n If the application doesn’t need the wake up capability of the AS8530, a direct connection EN to VCC is possible. In this case the AS8530 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via. VSUP signal as shown below. Figure 13. Permanent Normal Mode 8.7 Serial Port Interface The interface is essentially used to trigger the window watchdog, to access test mode and read out diagnostic information for the AS8530. The description of this interface and the protocol is explained below. Information on block status and errors can be displayed by diagnosis registers. 8.7.1 Device Configuration using 2-Wire Serial Port The AS8530 device configuration register is programmed via a 2-wire Serial Programming Interface. EN/SCL is used as Serial Clock and TX/ SDA_IO is used as Serial Data. EN is used as clock input to access serial port registers in serial port mode. Also EN is used to control transition from normal mode to standby/sleep mode. The TX input of the device will be multiplexed as following: LIN TX for transmitting data from microcontroller on LIN bus SDA_IO for Serial data input/output, this will be used for serially accessing data from configuration and status register 8.7.1.1 SP Frame A frame is formed by first byte for command and address/configuration and following bit stream that can be formed by an integer number of bytes. Command is coded RD/WR on the first bits, length of the transfer is indicated by LEN1, LEN2 bits while address is given on LSB 5 bits. Table 15. Command Bits Command Bits Register Address or Transmission Configuration RD/WR LEN1 LEN2 A4 A3 A2 A1 A0 RD/WR Command <A4:A0> Description 0 WRITE ADDRESS Writes data byte on the given starting address. 1 READ ADDRESS Read data byte from the given starting address. Table 16. Transfer Length LEN1 LEN2 Length Description 001 Transfer consists of single Data phase. After completion of single Data phase device comes out of Serial port interface. 0 1 2 Transfer consist of two Data phase. 1 0 4 Transfer consist of four Data phase. 1 1 8 Transfer consist of eight Data phase. EN VSUP VSS VCC RESET RX TX AS8530 MCU + 5V Cload VBAT LIN + |
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