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AS8530

Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.2 Wake-Up

If the regulator is put into sleep/standby mode, it can be woken up with the BUS interface. A transition on the BUS (high to low) with a minimum

8.3 Over-Temperature Shutdown

AS8530 will be initialized again. This initialization starts independently from the voltage levels on EN and BUS. Within the thermal shutdown

mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. The operation of the AS8530 is possible

initializes as explained in Initialization on page 17. The low slew mode for LIN Transceiver has to be selected again on re-initialization, if

necessary.

8.4 LIN BUS Transceiver

The AS8530 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The

transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed

by a de-bouncing unit.

8.4.1 Transmit Mode

During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic

emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.

Transmitting will be interrupted in the following cases:

Sleep mode

Thermal Shutdown active

Master Reset (VSUP < Vsuvr_on)

The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse

current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the

AS8530 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k

Ω resistor in

series with a diode to VBAT.

8.4.2 Receive Mode

The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the

implemented de-bouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely

observed.

RESET = Disabled

RESET = high-z

RESISTIVE DIVIDER = Disabled

VBAT = high, VBAT_DIV = low

Table 14. VSUP<Vsuvr_on

Block

Output Signal