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AS8530

Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.8 Control and Diagnosis Registers

The serial interface can be used as interface between the ASSP AS8530 and an external micro-controller. The interface is a slave and only the

micro-controller can start the communication. This interface will be used for device configuration, entering into test mode and carrying out

diagnostic options. Refer to Table 17 for details on the configuration registers.

8.8.1 Definition of Control and Status Registers

A total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 2-wire serial interface. Table 17 provides a description

of all control and status registers.

Table 17. Configuration Registers

Addr

Register

Name

POR Value

Bit

Type

Description

Control and Configuration Register

0 x 02

OTP Interface

Control

Register

On

POR_VCC

0000_0000

b[7:1]

R/W

Reserved

b[0]

OTP feature is only for factory use!

0

OTP interface is disabled.

1

OTP interface is enabled. When this bit is set, EN, TX, RX are used as

OTP interface pads. These pads can be used for OTP programming. OTP

interface is disabled on seeing high to low transition on RX (MODE).

0 x 03

Device

Configuration

Register

On

POR_VCC

0000_1011

b[7:4]

R/W

Reserved

b[3]

0

LIN Transceiver disabled

1

LIN Transceiver enabled

b[2]

0

Over-Temperature Monitor disabled

1

Over-Temperature Monitor enabled

b[1]

0

Low side Driver2 disabled

1

Low side Driver2 enabled

b[0]

0

Low side Driver1 disabled

1

Low side Driver1 enabled

0 x 04

Device

Control

Register

On

POR_VSUP

0000_0001

b[7:1]

R/W

Reserved

b[0]

Slew control

0

Low Slew Mode

1

High Slew mode

0 x 05

Temporary

Shutdown

Register

On

POR_VCC

0000_0000

b[7:1]

R/W

Reserved

b[0]

Temporary shutdown control bit

0

No Temporary shutdown

1

Enter into Temporary shutdown

0 x 06

Window

Watch Dog

Trigger

Register

On

POR_VCC

0000_0000

b[7:1]

W

Reserved

b[0]

Window Watch Dog Trigger. This bit will be set by MCU to indicate trigger event. If

this trigger occurs outside the Window of Watchdog counter, then RESET signal is

asserted. Also on this trigger WWD counter is restarted and this bit will be cleared

internally within 2 cycles of 128kHz clock.

0 x 07

Low Side

Driver Data

Register

On

POR_VCC

0000_0000

b[7:2]

R/W

Reserved

b[1]

This bit is Data input to Low Side Driver 2 gate input

b[0]

This bit is Data input to Low Side Driver 1 gate input