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AM1806 数据表(PDF) 71 Page - Texas Instruments |
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AM1806 数据表(HTML) 71 Page - Texas Instruments |
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71 / 241 page  0.1 µF 0.01 µF 50R 1.14V-1.32V 50R VSS PLLn_VDDA PLLn_VSSA FerriteBead:MurataBLM31PG500SN1L orEquivalent AM1806 www.ti.com SPRS658B – FEBRUARY 2010 – REVISED MAY 2010 6.6.1 PLL Device-Specific Information The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8. Figure 6-8. PLL External Filtering Components The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology. The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 71 Submit Documentation Feedback Product Folder Link(s): AM1806 |
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