AM1806 datasheet(78/241 Pages) TI

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AM1806

SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

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Table 6-6. AINTC System Interrupt Assignments (continued)

System Interrupt

Interrupt Name

Source

uPP_ALLINT

uPP Combined Interrupt

•

Channel I End-of-Line Interrupt

•

Channel I End-of-Window Interrupt

•

Channel I DMA Access Interrupt

•

Channel I Overflow-Underrun Interrupt

•

Channel I DMA Programming Error Interrupt

•

Channel Q End-of-Line Interrupt

•

Channel Q End-of-Window Interrupt

•

Channel Q DMA Access Interrupt

•

Channel Q Overflow-Underrun Interrupt

•

Channel Q DMA Programming Error Interrupt

VPIF_ALLINT

VPIF Combined Interrupt

•

Channel 0 Frame Interrupt

•

Channel 1 Frame Interrupt

•

Channel 2 Frame Interrupt

•

Channel 3 Frame Interrupt

•

Error Interrupt

EDMA3_1_CC0_INT0

EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer

Completion Interrupt

EDMA3_1_CC0_ERRINT

EDMA3_1Channel Controller 0 Error Interrupt

EDMA3_1_TC0_ERRINT

EDMA3_1 Transfer Controller 0 Error Interrupt

T64P3_ALL

Timer64P 3 - Combined TINT12 and TINT34

MCBSP0_RINT

McBSP0 Receive Interrupt

MCBSP0_XINT

McBSP0 Transmit Interrupt

MCBSP1_RINT

McBSP1 Receive Interrupt

100

MCBSP1_XINT

McBSP1 Transmit Interrupt

Peripheral Information and Electrical Specifications

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