AM1806 datasheet(95/241 Pages) TI

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AM1806

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SPRS658B – FEBRUARY 2010 – REVISED MAY 2010

6.10.5 EMIFA Electrical Data/Timing

Table 6-19 through Table 6-22 assume testing over recommended operating conditions.

Table 6-19. Timing Requirements for EMIFA SDRAM Interface

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Input setup time, read data valid on EMA_D[15:0] before

tsu(EMA_DV-EM_CLKH)

EMA_CLK rising

Input hold time, read data valid on EMA_D[15:0] after

th(CLKH-DIV)

1.6

EMA_CLK rising

Table 6-20. Switching Characteristics for EMIFA SDRAM Interface

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(CLK)

Cycle time, EMIF clock EMA_CLK

tw(CLK)

Pulse width, EMIF clock EMA_CLK high or low

td(CLKH-CSV)

Delay time, EMA_CLK rising to EMA_CS[0] valid

9.5

toh(CLKH-CSIV)

Output hold time, EMA_CLK rising to EMA_CS[0] invalid

td(CLKH-DQMV)

Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid

9.5

Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0]

toh(CLKH-DQMIV)

invalid

Delay time, EMA_CLK rising to EMA_A[12:0] and

td(CLKH-AV)

9.5

EMA_BA[1:0] valid

Output hold time, EMA_CLK rising to EMA_A[12:0] and

toh(CLKH-AIV)

EMA_BA[1:0] invalid

td(CLKH-DV)

Delay time, EMA_CLK rising to EMA_D[15:0] valid

9.5

toh(CLKH-DIV)

Output hold time, EMA_CLK rising to EMA_D[15:0] invalid

td(CLKH-RASV)

Delay time, EMA_CLK rising to EMA_RAS valid

9.5

toh(CLKH-RASIV)

Output hold time, EMA_CLK rising to EMA_RAS invalid

td(CLKH-CASV)

Delay time, EMA_CLK rising to EMA_CAS valid

9.5

toh(CLKH-CASIV)

Output hold time, EMA_CLK rising to EMA_CAS invalid

td(CLKH-WEV)

Delay time, EMA_CLK rising to EMA_WE valid

9.5

toh(CLKH-WEIV)

Output hold time, EMA_CLK rising to EMA_WE invalid

tdis(CLKH-DHZ)

Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated

9.5

tena(CLKH-DLZ)

Output hold time, EMA_CLK rising to EMA_D[15:0] driving

Peripheral Information and Electrical Specifications

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