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AM1806 数据表(PDF) 72 Page - Texas Instruments |
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AM1806 数据表(HTML) 72 Page - Texas Instruments |
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72 / 241 page  PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 DIV4.5 1 0 EMIFA Internal Clock Source CFGCHIP3[EMA_CLKSRC] 1 0 PREDIV PLLM 1 0 Square Wave Crystal PLL1_SYSCLK3 PLLCTL[EXTCLKSRC] AUXCLK PLL PLLDIV3 (/3) SYSCLK3 DDR2/mDDR Internal Clock Source PLLDIV2 (/2) PLLDIV3 (/3) PLLDIV1 (/1) 0 1 PLLCTL[PLLEN] POSTDIV PLLM PLL 0 1 PLLCTL[PLLEN] PLLCTL[CLKMODE] POSTDIV PLLC0 OBSCLK (CLKOUT Pin) DIV4.5 OSCDIV PLL Controller 0 PLL Controller 1 SYSCLK2 SYSCLK3 SYSCLK1 OSCIN 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 PLLC1 OBSCLK OCSEL[OCSRC] 14h 17h 18h 19h SYSCLK1 SYSCLK2 SYSCLK3 OCSEL[OCSRC] OSCDIV PLLC1 OBSCLK AM1806 SPRS658B – FEBRUARY 2010 – REVISED MAY 2010 www.ti.com Figure 6-9. PLL Topology 72 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1806 |
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