CS4294SLASHCS4298 datasheet(20/81 Pages) CIRRUS

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CS4205

DS489PP4

4.1

AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4205 from the AC ’97

controller. Figure 14 illustrates the serial port timing.

The PCM playback data being passed to the CS4205 is shifted out MSB first in the most significant bits

of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in

its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

4.1.1

Serial Data Output Slot Tags (Slot 0)

Valid Frame

The Valid Frame bit determines if any of the following slots contain either valid playback data

for the CS4205 or data for read/write operations. When ‘set’, at least one of the other AC-link

slots contains valid data. If this bit is ‘clear’, the remainder of the frame is ignored.

Slot 1 Valid

The Slot 1 Valid bit indicates a valid register read/write address for a primary codec.

Slot 2 Valid

The Slot 2 Valid bit indicates valid register write data for a primary codec.

Slot [3:11] Valid

The Slot [3:11] Valid bits indicate the validity of data in their corresponding serial data output

slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’, the

corresponding slot will be ignored.

Slot 12 Valid

The Slot 12 Valid bit indicates if output Slot 12 contains valid GPIO control data.

Codec ID[1:0]

The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link

frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01,

10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID

value of 01, 10, or 11 also indicates a valid read/write address and/or valid register write data

for a secondary codec.

4.1.2

Command Address Port (Slot 1)

R/W

Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index

bits will occur in the AC ’97 2.x audio codec. When the bit is ‘cleared’, a write will occur. For

any read or write access to occur, the Valid Frame bit (F0) must be ‘set’ and the Codec ID[1:0]

bits (F[14:15]) must match the Codec ID of the AC ’97 2.x audio codec being accessed. Ad-

ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and

both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For

a secondary codec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’

for read and write accesses. See Figure 14 for bit frame positions.

RI[6:0]

CS4205. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’

to access CS4205 registers.

Bit 15

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

Res

Codec

ID1

Codec

ID0

Bit 19

R/W

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Reserved

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