CS4294SLASHCS4298 datasheet(37/81 Pages) CIRRUS

37 / 81 page

CS4205

DS489PP4

5.16

Extended Audio Status/Control Register (Index 2Ah)

PRL

Mic ADC Powerdown. When ‘set’, the PRL bit powers down the dedicated Mic ADC and cor-

responding input gain stage. To use the dedicated Mic ADC, clear the PRL bit first.

MADC

Mic ADC Ready Status. When ‘set’, the MADC bit indicates the dedicated Mic ADC is ready

to transmit data.

VRM

Enable Variable Rate Mic Audio. When ‘set’, the VRM bit allows access to the Mic ADC Rate

VRM bit also serves as a powerdown for the Mic ADC SRC block. Clearing VRM will reset the

Mic ADC Rate Register (Index 34h) to its default value and the SRC data path is flushed.

VRA

Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC

Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must

be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as

a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC

Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default

values. The SRC data path is flushed and the Slot Request bits for the currently active DAC

slots will be fixed at ‘0’.

Default

4000h

D15

D14

D13

D12

D11

D10

PRL

MADC

VRM

VRA

CS4294/CS4298 数据表(PDF) 37 Page - Cirrus Logic