CS4294SLASHCS4298 datasheet(35/81 Pages) CIRRUS

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CS4205

DS489PP4

5.14

Powerdown Control/Status Register (Index 26h)

EAPD

External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power

down external amplifiers. The EAPD bit is mutually exclusive with the SDSC bit in the Serial

Port Control Register (Index 6Ah). The SDSC bit must be ‘clear’ before the EAPD bit may be

‘set’. If the SDSC bit is ‘set’, EAPD is a read-only bit and always returns ‘0’.

PR5

Internal Clock Disable. When ‘set’, the internal master clock is disabled (BIT_CLK running).

The only way to recover from setting this bit is through a Cold Reset (driving the RESET# sig-

nal active).

PR4

AC-link Powerdown. When ‘set’, the AC-link is powered down (BIT_CLK off). The AC-link can

be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RE-

SET# signal (primary audio codec only).

PR3

Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are

powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked be-

fore writing any mixer registers.

PR2

Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the volt-

age reference is still active). When clearing this bit, the ANL bit should be checked before writ-

ing any mixer registers.

PR1

Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the

DAC bit should be checked before sending any data to the DACs.

PR0

L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are

powered down. When clearing this bit, no valid data will be sent down the AC-link until the

ADC bit goes high.

REF

Voltage Reference Ready Status. When ‘set’, the REF bit indicates the voltage reference is

at a nominal level.

ANL

Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-

trols are ready. When ‘clear’, no volume control registers should be written.

DAC

Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC-link.

When ‘clear’, the DACs will not accept any valid data.

ADC

L/R ADCs Ready Status. When ‘set’, the ADCs are ready to send data across the AC-link.

When ‘clear’, no data will be sent to the controller.

Default

0000h. This value indicates all blocks are powered on. The lower four bits will change as the

CS4205 finishes an initialization and calibration sequence.

The PR[5:0] and the EAPD bits are powerdown control for different sections of the CS4205 as well as external am-

plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec-

tion of the CS4205 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must

be checked before writing to any mixer registers. See Section 10, Power Management, for more information on the

powerdown functions.

D15

D14

D13

D12

D11

D10

EAPD

PR5

PR4

PR3

PR2

PR1

PR0

REF

ANL

DAC

ADC

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