CS4294SLASHCS4298 datasheet(23/81 Pages) CIRRUS

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CS4205

DS489PP4

4.2.3

Status Data Port (Slot 2)

RD[15:0]

Read Data. The RD[15:0] bits contain the register data requested by the controller from the

previous read request. All read requests will return the read address in the input Slot 1 and

the register data in the input Slot 2 on the following serial data frame.

4.2.4

PCM Capture Data (Slot 3-8,11)

CD[17:0]

Capture Data. The CD [17:0] bits contain 18-bit PCM (2’s complement) capture data. The

data will only be valid when the respective slot valid bit is ‘set’ in input Slot 0. The mapping of

a given slot to an ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID

5Eh). The definition of each slot can be found in Table 14 on page 43.

4.2.5

GPIO Pin Status (Slot 12)

GPIO[4:0]

GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4205 GPIO pins configured

as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the

GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the

GPIO[4:0] pin control bits in output Slot 12.

BDI

BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic

OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the

BDI Config Register (Index 6Eh, Address 0Ch).

IEC

Internal Error Condition. The IEC bit indicates that an internal error, such as an ADC over-

range or a digital data overflow has occurred. This bit is a logic OR of all bits in the IEC Status

GPIO_INT

GPIO Interrupt. The GPIO_INT bit indicates that a GPIO, BDI, or IEC interrupt event has oc-

curred. The occurrence of a GPIO interrupt is determined by the GPIO interrupt requirements

as outlined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the

GPIO_INT bit is cleared by writing a ‘0’ to the bit in the GPIO Pin Status Register (Index 54h)

corresponding to the GPIO pin which generated the interrupt.

The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined

in the BDI Control Registers (Index 6Eh, Address 0Ch - 0Dh). In this case, the GPIO_INT bit

is cleared by writing a ‘0’ to the bit in the BDI Status Register (Index 7Ah) that generated the

interrupt.

The occurrence of an IEC interrupt is determined by the IEC interrupt requirements as out-

lined in the Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh).

In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the IEC Status Register

(Index 6Eh, Address 0Bh) corresponding to the IEC source which generated the interrupt.

Bit 19

3210

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Reserved

Bit 19

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

Bit 19 18

87654

GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Res BDI IEC

GPIO

_INT

CS4294/CS4298 数据表(PDF) 23 Page - Cirrus Logic

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