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PIC12F1822-I/MF 数据表(PDF) 314 Page - Microchip Technology |
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PIC12F1822-I/MF 数据表(HTML) 314 Page - Microchip Technology |
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314 / 398 page  PIC12F/LF1822/16F/LF1823 DS41413A-page 314 Preliminary 2010 Microchip Technology Inc. TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0(1) R/W-0/0 R/W-0/0 R/W-0/0 — — — — CPSCH<3:2>(2) CPSCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4)(1) 0101 = channel 5, (CPS5)(1) 0110 = channel 6, (CPS6)(1) 0111 = channel 7, (CPS7)(1) 1000 = Reserved. Do not use. • • • 1111 = Reserved. Do not use. Note 1: These channels are only implemented on the PIC16F/LF1823. 2: PIC16F/LF1823 only. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — —ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 126 CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 313 CPSCON1 — — — — CPSCH3(1) CPSCH2(1) CPSCH1 CPSCH0 314 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 89 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 171 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON 180 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 121 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 125 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module. Note 1: PIC16F/LF1823 only. |
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