PIC12F1822-ISLASHMF datasheet(71/398 Pages) MICROCHIP

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Preliminary

DS41413A-page 71

PIC12F/LF1822/16F/LF1823

6.0

REFERENCE CLOCK MODULE

The reference clock module provides the ability to send

a divided clock to the clock output pin of the device

(CLKR) and provide a secondary internal clock source

to the modulator module. This module is available in all

oscillator configurations and allows the user to select a

greater range of clock submultiples to drive external

devices in the application. The reference clock module

includes the following features:

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

• Slew rate control

The reference clock module is controlled by the CLKR-

CON register (Register 6-1) and is enabled when set-

ting the CLKREN bit. To output the divided clock signal

to the CLKR port pin, the CLKROE bit must be set. The

CLKRDIV<2:0> bits enable the selection of 8 different

clock divider options. The CLKRDC<1:0> bits can be

used to modify the duty cycle of the output clock(1). The

CLKRSLR bit controls slew rate limiting.

For information on using the reference clock output

with the modulator module, see Section 22.0 “Data

Signal Modulator”.

6.1

Slew rate

The slew rate limitation on the output port pin can be

disabled. The Slew Rate limitation can be removed by

clearing the CLKRSLR bit in the CLKRCON register.

6.2

Effects of a Reset

Upon any device Reset, the reference clock module is

disabled. The user’s firmware is responsible for

initializing the module before enabling the output. The

registers are reset to their default values.

6.3

Conflicts with the CLKR pin

There are two cases when the reference clock output

signal cannot be output to the CLKR pin, if:

• LP, XT, or HS oscillator mode is selected.

• CLKOUT function is enabled.

Even if either of these cases are true, the module can

still be enabled and the reference clock signal may be

used in conjunction with the modulator module.

6.3.1

OSCILLATOR MODES

If LP, XT, or HS oscillator modes are selected, the

OSC2/CLKR pin must be used as an oscillator input pin

and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more informa-

tion on different oscillator modes.

6.3.2

CLKOUT FUNCTION

The CLKOUT function has a higher priority than the

reference clock module. Therefore, if the CLKOUT

function is enabled by the CLKOUTEN bit in Configura-

tion Word 1, FOSC/4 will always be output on the port

pin. Reference Section 4.0 “Device Configuration”

for more information.

6.4

Operation During Sleep

As the reference clock module relies on the system

clock as its source, and the system clock is disabled in

Sleep, the module does not function in Sleep, even if

an external clock source or the Timer1 clock source is

configured as the system clock. The module outputs

will remain in their current state until the device exits

Sleep.

Note 1: If the base clock rate is selected without a

divider, the output clock will always have

a duty cycle equal to that of the source

clock, unless a 0% duty cycle is selected.

If the clock divider is set to base clock/2,

then 25% and 75% duty cycle accuracy

will be dependent upon the source clock.

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