PIC12F1822-ISLASHMF datasheet(91/398 Pages) MICROCHIP

91 / 398 page

 2010 Microchip Technology Inc.

Preliminary

DS41413A-page 91

PIC12F/LF1822/16F/LF1823

8.5.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 8-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

U-0

OSFIE

C2IE(1)

C1IE

EEIE

BCL1IE

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt

0 = Disables the Oscillator Fail interrupt

bit 6

C2IE: Comparator C2 Interrupt Enable bit(1)

1 = Enables the Comparator C2 interrupt

0 = Disables the Comparator C2 interrupt

bit 5

C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt

0 = Disables the Comparator C1 interrupt

bit 4

EEIE: EEPROM Write Completion Interrupt Enable bit

1 = Enables the EEPROM Write Completion interrupt

0 = Disables the EEPROM Write Completion interrupt

bit 3

BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt

0 = Disables the MSSP Bus Collision Interrupt

bit 2-0

Unimplemented: Read as ‘0’

Note 1:

PIC16F/LF1823 only.

PIC12F1822-I/MF 数据表(PDF) 91 Page - Microchip Technology

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