PIC12F1822-ISLASHMF datasheet(336/398 Pages) MICROCHIP

336 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 336

Preliminary

 2010 Microchip Technology Inc.

29.1

DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Industrial, Extended)

PIC12LF1822/16LF1823

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +85°C for industrial

-40°C

 TA  +125°C for extended

PIC12F1822/16F1823

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +85°C for industrial

-40°C

 TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

D001

VDD

Supply Voltage

PIC12LF1822/16LF1823

1.8

2.3

—

3.6

FOSC

 16 MHz:

FOSC

 32 MHz (NOTE 2)

D001

PIC12F1822/16F1823

1.8

2.3

—

5.5

FOSC

 16 MHz:

FOSC

 32 MHz (NOTE 2)

D002*

VDR

RAM Data Retention Voltage(1)

PIC12LF1822/16LF1823

1.5

—

Device in Sleep mode

D002*

PIC12F1822/16F1823

1.7

—

Device in Sleep mode

VPOR*

Power-on Reset Release Voltage

—1.6

—

VPORR*

Power-on Reset Rearm Voltage

PIC12LF1822/16LF1823

—

0.8

—

Device in Sleep mode

PIC12F1822/16F1823

—

1.7

—

Device in Sleep mode

D003

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

-5.5

-6.0

-5.5

-6.0

-5.5

-6.0

5.5

1.024V, VDD

 2.5V, 85°C

1.024V, VDD

 2.5V, 125°C

2.048V, VDD

 2.5V, 85°C

2.048V, VDD

 2.5V, 125°C

4.096V, VDD

 4.75V, 85°C

4.096V, VDD

 4.75V, 125°C

VCDAFVR

Fixed Voltage Reference Voltage for

Comparator and DAC, Initial Accu-

racy

-5.5

-6.0

-5.5

-6.0

-5.5

-6.0

5.5

1.024V, VDD

 2.5V, 85°C

1.024V, VDD

 2.5V, 125°C

2.048V, VDD

 2.5V, 85°C

2.048V, VDD

 2.5V, 125°C

4.096V, VDD

 4.75V, 85°C

4.096V, VDD

 4.75V, 125°C

D004*

SVDD

VDD Rise Rate to ensure internal

Power-on Reset signal

0.05

—

V/ms See Section 7.1 “Power-on Reset

(POR)” for details.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PLL required for 32 MHz operation.

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