PIC12F1822-ISLASHMF datasheet(106/398 Pages) MICROCHIP

106 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 106

Preliminary

 2010 Microchip Technology Inc.

11.3

Flash Program Memory Overview

It is important to understand the Flash program mem-

ory structure for erase and programming operations.

Flash Program memory is arranged in rows. A row con-

sists of a fixed number of 14-bit program memory

words. A row is the minimum block size that can be

erased by user software.

Flash program memory may only be written or erased

if the destination address is in a segment of memory

that is not write-protected, as defined in bits WRT<1:0>

of Configuration Word 2.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the EEDATH:EEDATL register pair.

The number of data write latches is not equivalent to

the number of row locations. During programming, user

software will need to fill the set of write latches and ini-

tiate a programming operation multiple times in order to

fully reprogram an erased row. For example, a device

with a row size of 32 words and eight write latches will

need to load the write latches with data and initiate a

programming operation four times.

The size of a program memory row and the number of

program memory write latches may vary by device.

See Table 11-1 for details.

11.3.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

Write the Least and Most Significant address

bits to the EEADRH:EEADRL register pair.

Clear the CFGS bit of the EECON1 register.

Set the EEPGD control bit of the EECON1

Then, set control bit RD of the EECON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF EECON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the EEDATH:EEDATL register pair; therefore, it can

be read as two bytes in the following instructions.

EEDATH:EEDATL register pair will hold this value until

another read or until it is written to by the user.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

TABLE 11-1:

FLASH MEMORY

ORGANIZATION BY DEVICE

Device

Erase Block

(Row) Size/

Boundary

Number of

Write Latches/

Boundary

PIC12F/LF1822/

16F/LF1823

16 words,

EEADRL<3:0>

= 0000

16 words,

EEADRL<3:0>

= 0000

Note 1: The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle

instruction

the

instruction after the RD bit is set.

2: Flash program memory can be read

regardless of the setting of the CP bit.

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