MC68HC705MC4MP datasheet(139/180 Pages) FREESCALE

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General Release Specification

Core Timer

General Release Specification — MC68HC705MC4

Section 12. Core Timer

12.1 Contents

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

12.3

Ctimer Control and Status Register . . . . . . . . . . . . . . . . . . . .141

12.4

Computer Operating Properly (COP) Watchdog Reset . . . . .143

12.5

Ctimer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

12.6

Core Timer during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . .144

12.2 Introduction

The core timer (Ctimer) for this device is a 15-stage multi-functional

ripple counter. The features include timer overflow, power-on reset

(POR), real time interrupt, and COP watchdog timer

As seen in Figure 12-1, the core timer is driven by the internal bus clock

divided by four as a fixed prescaler. This signal drives an 8-bit ripple

counter. The value of this 8-bit ripple counter can be read by the CPU at

any time by accessing the Ctimer counter register (CTCR) at address

$09. A timer overflow function is implemented on the last stage of this

counter, giving a possible interrupt at the rate of E/1024. Two additional

stages produce the POR function at E/4064. The timer counter bypass

circuitry (available only in test mode) is at this point in the timer chain.

This circuit is followed by one more stage, with the resulting clock

(E/8192) driving the real-time interrupt circuit. The RTI circuit consists of

four divider stages with a 1-of-4 selector. The output of the RTI circuit is

further divided by eight to drive the mask optional COP watchdog timer

circuit. The RTI rate selector bits and the RTI and CTOF enable bits and

flags are located in the Ctimer control and status register (CTCSR) at

location $08.

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