CDCE925

CDCEL925

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SCAS847F – JULY 2007 – REVISED MARCH 2010

TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating free-air temperature

MIN

NOM

MAX

UNIT

CLK_IN REQUIREMENTS

PLL bypass mode

0

160

LVCMOS clock input frequency

MHz

PLL mode

8

160

Rise and fall time CLK signal (20% to 80%)

3

ns

40%

60%

STANDARD

FAST

MODE

MODE

UNIT

MIN

MAX

MIN

MAX

SDA/SCL TIMING REQUIREMENTS (see Figure 12)

SCL clock frequency

0

100

0

400

kHz

START setup time (SCL high before SDA low)

4.7

0.6

ms

START hold time (SCL low after SDA low)

4

0.6

ms

SCL low-pulse duration

4.7

1.3

ms

SCL high-pulse duration

4

0.6

ms

SDA hold time (SDA valid after SCL low)

0

3.45

0

0.9

ms

SDA setup time

250

100

ns

SCL/SDA input rise time

1000

300

ns

SCL/SDA input fall time

300

300

ns

STOP setup time

4

0.6

ms

Bus free time between a STOP and START condition

4.7

1.3

ms

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