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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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CDCE925PW 数据表(PDF) 22 Page - Texas Instruments |
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CDCE925PW 数据表(HTML) 22 Page - Texas Instruments |
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22 / 27 page  CDCE925 CDCEL925 SCAS847F – JULY 2007 – REVISED MARCH 2010 www.ti.com REVISION HISTORY Changes from Original (July 2007) to Revision A Page • Changed the data sheet status From: Product Preview To: Production data. ..................................................................... 1 Changes from Revision A (August 2007) to Revision B Page • Changed IDDPD Power-down current Typ value From: 20 To: 30 .......................................................................................... 6 • Changed II LVCMOS Input current value From: ±5 Typ To: ±5 Max .................................................................................... 6 • Changed IIH LVCMOS Input current for S0/S1/S2 value From: 5 Typ To: 5 Max ................................................................ 6 • Changed IIL LVCMOS Input current for S0/S1/S2 value From: -4 Typ To: -4 Max .............................................................. 6 • Changed text of Note 4 in the DEVICE CHARACTERISTIC table ....................................................................................... 7 • Changed Figure 2, Test Load for 50- Ω Board Environment ................................................................................................. 8 • Changed Table 2 header From: OUTPUT SELECTION (Y2 ... Y9) To: OUTPUT SELECTION (Y2 ... Y5) ...................... 10 • Changed Table 9 - 01h Bit 7 From: For interla use – always write To: Reserved – always write ..................................... 16 • Changed Table 9 - PLL2_1N [11:4] description From: fVCO1_1 To: fVCO2_1 .......................................................................... 20 Changes from Revision B (August 2007) to Revision C Page • Changed the PACKAGE THERMAL RESISTANCE for TSSOP table ................................................................................. 3 • Changed Table 9 - RID From: 0h To: Xb ........................................................................................................................... 16 • Added note to the PWDN description, Table 9 ................................................................................................................... 16 Changes from Revision C (December 2007) to Revision D Page • Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. .................. 3 Changes from Revision D (September 2009) to Revision E Page • Deleted sectence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information. .................................................................................................... 11 Changes from Revision E (October 2009) to Revision F Page • Added PLL settings limits: 16 ≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 to PLL1 and PLL2 Configure Register tables ............. 18 • Added PLL settings limits: 16 ≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<511 to PLL Multiplier/Divder Definition Section .................... 21 22 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE925 CDCEL925 |
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