CDCE925

CDCEL925

www.ti.com

SCAS847F – JULY 2007 – REVISED MARCH 2010

SDA/SCL CONFIGURATION REGISTERS

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and

explanations describe the programmable functions of the CDCE925/CDCEL925. All settings can be manually

written into the device via the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI

Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for

optimized performance at lowest jitter.

Table 7. SDA/SCL Registers

Address Offset

Register Description

Table

00h

Generic Configuration Register

Table 9

10h

PLL1 Configuration Register

Table 10

20h

PLL2 Configuration Register

Table 11

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the

Control Terminal Register. The user can predefine up to eight different control settings. These settings then can

be selected by the external control pins, S0, S1, and S2. Table 8 explains the corresponding bit assignment

between the Control Terminal Register and the Configuration Registers.

Table 8. Configuration Register, External Control Terminals

Y1

PLL1 Settings

PLL2 Settings

Output

Frequency

SSC

Output

Frequency

SSC

Output

External Control Pins

Selection

Selection

Selection

Selection

Selection

Selection

Selection

S2

S1

S0

Y1

FS1

SSC1

Y2Y3

FS2

SSC2

Y4Y5

0

0

0

0

Y1_0

FS1_0

SSC1_0

Y2Y3_0

FS2_0

SSC2_0

Y4Y5_0

1

0

0

1

Y1_1

FS1_1

SSC1_1

Y2Y3_1

FS2_1

SSC2_1

Y4Y5_1

2

0

1

0

Y1_2

FS1_2

SSC1_2

Y2Y3_2

FS2_2

SSC2_2

Y4Y5_2

3

0

1

1

Y1_3

FS1_3

SSC1_3

Y2Y3_3

FS2_3

SSC2_3

Y4Y5_3

4

1

0

0

Y1_4

FS1_4

SSC1_4

Y2Y3_4

FS2_4

SSC2_4

Y4Y5_4

5

1

0

1

Y1_5

FS1_5

SSC1_5

Y2Y3_5

FS2_5

SSC2_5

Y4Y5_5

6

1

1

0

Y1_6

FS1_6

SSC1_6

Y2Y3_6

FS2_6

SSC2_6

Y4Y5_6

7

1

1

1

Y1_7

FS1_7

SSC1_7

Y2Y3_7

FS2_7

SSC2_7

Y4Y5_7

04h

13h

10h–12h

15h

23h

20h–22h

25h

(1)

Address Offset refers to the byte address in the Configuration Register in Table 9, Table 10, and Table 11.

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