CDCE925

CDCEL925

SCAS847F – JULY 2007 – REVISED MARCH 2010

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SDA/SCL SERIAL INTERFACE

This section describes the SDA/SCL interface of the CDCE925/CDCEL925 device. The CDCE925/CDCEL925

specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode transfer (up to 400 kbit/s)

and supports 7-bit addressing.

The SDA/S1 and SCL/S2 pins of the CDCE925/CDCEL925 are dual-function pins. In the default configuration

they are used as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control

pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

DATA PROTOCOL

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with

most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of

bytes read out are defined by byte count in the Generic Configuration Register. At Block Read instruction all

bytes defined in the byte count has to be read out to correctly finish the read cycle.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to

each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write

Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read

out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by

EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 5.

Table 5. Slave Receiver Address (7 Bits)

DEVICE

A6

A5

A4

A3

A2

R/W

CDCE913/CDCEL913

1

1

0

0

1

0

1

1/0

CDCE925/CDCEL925

1

1

0

0

1

0

0

1/0

CDCE937/CDCEL937

1

1

0

1

1

0

1

1/0

CDCE949/CDCEL949

1

1

0

1

1

0

0

1/0

(1)

Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to four devices connected

to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.

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