1

7

1

1

1

1

1

1

S

Slave Address

Wr

A

A

Sr

Rd

A

8

1

1

1

1

ByteCountN

A

A

A

P

DataByte0

…

DataByteN-1

8

CommandCode

7

Slave Address

8

8

P

S

P

SCL

SDA

VIH

VIL

VIH

VIL

A

Bit7(MSB)

Bit6

Bit0(LSB)

CDCE925

CDCEL925

Slave

Master

SDA

SCL

R

P

R

P

C

BUS

C

BUS

CDCE925

CDCEL925

SCAS847F – JULY 2007 – REVISED MARCH 2010

www.ti.com

Block Read Programming Sequence

Figure 11. Block Read Protocol

Timing Diagram for the SDA/SCL Serial Control Interface

Figure 12. Timing Diagram for SDA/SCL Serial Control Interface

SDA/SCL HARDWARE INTERFACE

Figure 13 shows how the CDCE925/CDCEL925 clock synthesizer is connected to the SDA/SCL serial interface

bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the

maximum) if many devices are connected.

devices. The recommended pullup value is 4.7 k

Figure 13. SDA / SCL Hardware Interface

14

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