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SA9101

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ADR 5

Data link bits for internal use

Bit

Description

Name

CR5B0

i (X)-bit in frame 15

Only if CRC4 processing activated and

Non- transparent or Extended TS0

CR5B1

i (X)-bit in frame 13

Signalling Transparent mode enabled.

CR5B2

i (X)-bit of frame alignment signal for international use, if

double frame format enabled and Non-transparent or Extended

TS0 Signalling Transparent mode enabled.

CR5B3

Automatic Transmission of Submultiframe Status (only in

CRC4

mode, and Non-transparent or Extended TS0 signalling

transparent mode).

Instead of transmitting Si bits (CR5 bit 0 and 1), the sub-

multiframe status is inserted (SR 8, bit 1 -> X-bit(13), SR8 bit 0

-> X-bit(15).

CR5B4

Timeslot 0 Signalling Transparent mode. In Double frame and

CRC Multiframe modes Sn and Si bits of Timeslot 0 are

transmitted as applied on DXI.

CR5B5

Timeslot 0 Full Transparent mode

All information is transmitted as applied on DXI.

CR5B6

Interrupt Mask “Begin

Receive Multiframe”

A “1” enables interrupt source

only if alarm interrupt mode

CR5B7

Interrupt Mask "Begin

enabled

Transmit Multiframe"

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