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ADR 1

Frame Error Counter

Bit

Description

Name

SR1B[0-7]

0-7

8 bit counter will be incremented when an incorrect frame

alignment word is detected in the synchronized state.

An overflow is inhibited.

During alarm simulation, the counter should increment every

250µs.

ADR 2

Code Violation Counter

Bit

Description

Name

SR2B[0-7]

0-7

8 bit counter which counts HDB3 code violations if no optical

interface mode has been enabled. An overflow is inhibited.

During alarm simulation, the counter should increment once

for every four bits received. Counter can be extended to 10 bits

by bit 3 of Extended Mode Register ADR1 (CX1B3).

ADR 3

CRC4 Error counter

Bit

Description

Name

SR3B[0-7]

0-7

8 bit counter which counts submultiframe CRC4 errors. An

overflow is inhibited.

During alarm simulation, the counter should increment once

per submultiframe.

The counter can be extended to a 10 bit counter by setting bit

7 of Receive Control Register ADR8 (CR8B7).

ADR 4

Received Service Word

Bit

Description

Name

SR4B[0-4]

0-4

Y-bits (Sn-bits) for national use

SR4B5

Bit 3 of service word (Receive Remote Alarm)

SR4B6

Fixed to “1”.

SR4B7

First bit in received service word. It is fixed to “1” if the device

is in CRC4-mode. Only used in Double Frame format.

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