SA9101 datasheet(6/40 Pages) SAMES

6 / 40 page

SA9101

sames

6/40

DESCRIPTION OF INTERFACES

Fibre Optical Interface

The fibre optical interface is enabled via the microprocessor interface.

Signal

Input/Output/Bidirect

Function

OPIN

Optical Fibre In

Unipolar Input Signal at 2048 kbps

Input polarity sense is programmable

via CR8B3.

Latching of data is

performed with the falling edge of

RCLK if optical interface is selected

via CR1B2. (See Fig. 6 Line Interface

Timing.)

OPOUT

Optical Fibre Out

Unipolar Output Signal at 2048 kbps

The output's active polarity is

programmable via CR6B7.

Data is

clocked out on the rising edge of

XRCLK.

Data duty cycle is 100%.

(See Fig. 6 Line Interface Timing.)

RCLK

Route Clock

This clock, derived from the incoming

data by the line interface circuit (eg.

IPAT (PEB2235)), is necessary for

clocking received data into the SA9101.

XRCLK

Transmit Route Clock

This 2048kHz clock is generated from

the Station Clock, SCLK. (See Fig. 5

System Interface Timing and Fig. 6

Line Interface Timing.)

PCM30 Interface

Signal

Input/Output/Bidirect

Function

DRA

27,

Data Receive +/-

DRB

HDB3 coded PCM Signal

DXA

38,

Data transmit +/-

DXB

HDB3 coded PCM Signal

RCLK

Route Clock f = 2.048 MHz

XRCLK

Transmit route clock

SA9101 数据表(PDF) 6 Page - Sames

SA9101 数据表(HTML) 6 Page - Sames

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载