430 datasheet(24/100 Pages) INTEL

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Electrical Specifications

Datasheet

NOTES:

Refer to Section 4.2 for signal descriptions.

In processor systems where no debug port is implemented on the system board, these

signals are used to support a debug port interposer. In systems with the debug port

implemented on the system board, these signals are no connects.

The value of these signals during the active-to-inactive edge of RESET# defines the

processor configuration options. See Section 6.1 for details.

PROCHOT# signal type is open drain output and CMOS input.

NOTES:

Signals that do not have RTT, nor are actively driven to their high-voltage level.

NOTE:

These signals also have hysteresis added to the reference voltage. See Table 12 for more

information.

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,

GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0],

VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,

VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI

Table 8.

FSB Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals1

Table 9.

Signal Characteristics

Signals with RTT

Signals with No RTT

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,

HITM#, LOCK#, PROCHOT#, REQ[4:0]#,

RS[2:0]#, TRDY#

A20M#, BCLK[1:0], BSEL[2:0],

COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],

LINT0/INTR, LINT1/NMI, PWRGOOD,

RESET#, SMI#, STPCLK#, TESTHI[13:0],

VID[6:0], GTLREF[1:0], TCK, TDI, TMS,

TRST#

Open Drain Signals1

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BR0#, TDO, VTT_SEL, FCx

Table 10.

Signal Reference Voltages

GTLREF

VTT/2

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

TRDY#

A20M#, LINT0/INTR, LINT1/NMI,

IGNNE#, INIT#, PROCHOT#,

PWRGOOD1, SMI#, STPCLK#, TCK1,

TDI1, TMS1, TRST#1

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