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430 数据表(PDF) 29 Page - Intel Corporation |
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430 数据表(HTML) 29 Page - Intel Corporation |
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29 / 100 page  Datasheet 29 Electrical Specifications 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The processor will operate at an 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency. 2.8.3 Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. Table 16. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L RESERVED L L H RESERVED L H H RESERVED LH L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED |
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