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ST10F276Z5 数据表(PDF) 12 Page - STMicroelectronics

部件名 ST10F276Z5
功能描述  16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM
PDF  239 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F276Z5 数据表(HTML) 12 Page - STMicroelectronics

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ST10F276Z5
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List of figures
Figure 1.
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2.
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4.
Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5.
ST10F276Z5 new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 6.
Booting steps for ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7.
Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 8.
Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 9.
UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 10.
Baud rate deviation between host and ST10F276Z5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 11.
CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 12.
Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 13.
Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 14.
CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 15.
MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 16.
X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 17.
Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 18.
Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 19.
Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 20.
Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 102
Figure 21.
Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 102
Figure 22.
Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 103
Figure 23.
Connection to one CAN bus with internal Parallel mode enabled . . . . . . . . . . . . . . . . . . 103
Figure 24.
Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 25.
Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 26.
Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 27.
Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 28.
Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 29.
Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 30.
Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 31.
Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 32.
SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 33.
SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 34.
SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 35.
SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36.
SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . 124
Figure 37.
Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 38.
System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 39.
Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 40.
Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 127
Figure 41.
Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 128
Figure 42.
PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 43.
External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 44.
Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 45.
Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 184
Figure 46.
A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 47.
A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 48.
Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 192



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