STE12PS datasheet(27/44 Pages) STMICROELECTRONICS

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STE12PS

I2C slave protocol overview

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I2C slave protocol overview

The interface is capable of recognizing its own address (7 bit).

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the

start condition contains the device address.

A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must

pull LOW the SDA line to acknowledge the transfer.

The speed of the I2C interface is fixed at Fast I2C, that is, 100 to 400 kHz.

5.1

Functional description

As soon as a start condition is detected, the address is received from the SDA line and sent

to a shift register; then it is compared with the internal address that is composed by the five

pins for the five LSB and by a hardwired value equal to “01” for the other two bits.

In case of address mismatch the interface ignores it and waits for another Start condition.

If address is matched the interface generates an acknowledge pulse.

Following the address reception, POE digital controller receives bytes from the SDA line into

the data register via an internal shift register or sends bytes from the data register to the

SDA line through the internal shift register. After each byte reception an acknowledge pulse

is generated by the controller.

A Stop condition generated by the host processor, after the last data byte is transferred,

closes the communication.

5.2

Error cases

An error state is generated when Stop or Start conditions are detected during a byte

transfer. If it is a Stop then the interface discards the data, releases the lines and waits for

another Start condition. If it is a Start then the interface discards the data and waits for the

next slave address on the bus.

5.3

Interrupts

Irq register bits indicate which signals can generate an interrupt. The register is read only

and to clear the interrupt bits the corresponding source event has to be cleared. The logic

OR condition of the interrupt bits causes the INTN pin assertion. The INTN assertion can be

masked via the interrupt mask register

Irq_mask.

5.4

I2C device address

The device is required to have an I²C address of: 01xxxxxb(A6 down to A0).

Pins I2C_ADDR[4:0] can be used to set the lower I2C address bits.

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