STE12PS datasheet(5/44 Pages) STMICROELECTRONICS

5 / 44 page

Obsolete

Product(s)

- Obsolete

Product(s)

STE12PS

Pin description

5/44

Pin description

Table 1.

Analog pins description

Pin name

I/O

Function

IDET_HVLV

Anti-aliasing filter capacitor to be connected between the analog input and

ground to improve ADC noise performance. C = 180pF.

IMON_HVLV

Anti-aliasing filter capacitor to be connected between the analog input and

ground. C = 180pF.

Vbat_mon

Anti-aliasing filter capacitor to be connected between the analog input and

ground. C = 100nF.

Vbatref

Anti-aliasing filter capacitor to be connected between the analog input and

ground. C = 100nF.

I_REF

Anti-aliasing filter capacitor to be connected between the analog input and

ground. C = 180pF.

CDETSLOW

Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms.

RSENSE

SMPS precision, external, current limiting reference resistor: 100m

VDRIVE

External p-channel MOSFET gate driving voltage for SMPS. It provides a

square wave with VL as upper limit and (VL-10V) as lower limit voltage.

SFTSTR

Switched Mode Power Supply (SMPS) soft start capacitor, 200nF.

SMPS feedback pin, Cfb = 2.2nF

Power DMOS device drain, if DMOS is turned-on, channel “n” where n = 1,…12

is activated.

ACSn

It provides a 50Hz AC disconnection signal for port “n”, n = 1, … 12.

SPn

Detection classification and AC disconnection sensing port “n”, n = 1, … 12.

SSRPn

Line current to the monitoring resistor for channel “n”, n = 1,… 12. Allowed

values are 0.523, 1.05, 1.58 and 2.1ohms (see also SENSPROG preset pins).

Sensing pin.

FSRPn

Source terminal for power DMOS connected to the sense resistor for channel

“n”, n = 1,… 12, a “forcing” pin.

RMONF

Mirror monitoring resistance (500

× Rsense) pin to let internal ADC evaluate line

currents. Forcing pin.

RMONS

Mirror monitoring resistance (500

× Rsense) pin to let internal ADC evaluate line

currents. A “sensing” pin.

RREF

Reference bias resistor: 18.7k

Ω

CLK_GEN1

Crystal oscillator pin1 for high performance clock generation.

CLK_GEN2

Crystal oscillator pin2 for high performance clock generation.

MCLK

Master clock output for multi device configuration.

CLK_GEN3

Low profile clock input pin or clock input pin in multi-device configuration.

ACin

50Hz sinusoidal input

ACout

50Hz sinusoidal output, internally generated

STE12PS 数据表(PDF) 5 Page - STMicroelectronics

STE12PS 数据表(HTML) 5 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

STE12PS 数据表(PDF) 5 Page - STMicroelectronics

STE12PS 数据表(HTML) 5 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载