MPC8343CVRADDB datasheet(60/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Clocking

As shown in Figure 36, the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following

equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the

csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL

multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),

which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,

clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock

subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])

ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (

÷2) to

create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the

same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])

lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create

the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is

controlled by LCCR[CLKDIV].

In addition, some of the internal units may have to be shut off or operate at lower frequency than the

csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped

All frequency combinations shown in the table below may not be available. Maximum operating

frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully Addressed by This

Document,” for part ordering details and contact your Freescale Sales Representative or authorized

distributor for more information.

Table 52. Configurable Clock Units

Unit

Default Frequency

Options

TSEC1

csb_clk/3

Off, csb_clk, csb_clk/2, csb_clk/3

TSEC2, I2C1

csb_clk/3

Off, csb_clk, csb_clk/2, csb_clk/3

Security core

csb_clk/3

Off, csb_clk, csb_clk/2, csb_clk/3

USB DR, USB MPH

csb_clk/3

Off, csb_clk, csb_clk/2, csb_clk/3

PCI and DMA complex

csb_clk

Off, csb_clk

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