MPC8343CVRADDB datasheet(77/79 Pages) FREESCALE

77 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Document Revision History

23 Document Revision History

Table 64 provides a revision history of this document.

Table 64. Document Revision History

Rev.

Number

Date

Substantive Change(s)

11/2010

• In Table 51, added overbar to LCS[4] and LCS[5] signals. In Table 51 added note for pin LGPL4.

•In Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins.

05/2010

• In Table 25 through Table 26, changed VIL(min) to VIH(max) to (20%–80%).

• Added Table 8, “EC_GTX_CLK125 AC Timing Specifications.”

5/2009

• In Section 18.1, “Package Parameters for the MPC8343EA PBGA, changed solder ball for TBGA

and PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.

•In Table 53, added two columns for the DDR1 and DDR2 memory bus frequency.

•In Table 62, footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1

and DDR2.

2/2009

• Added footnote 6 to Table 7.

•In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.

•In Table 35, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock

in DLL bypass mode). Similarly, made the same correction to Figure 17, Figure 19, and Figure 20

for output signals.

• Added footnote 10 to Table 51.

•In Table 51, updated note 11 to say the following: “SEC1_TXD[3] is required an external pull-up

resistor. For proper functionality of the device, this pin must be pulled up or actively driven high

during a hard reset. No external pull-down resistors are allowed to be attached to this net.”

•In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.

•In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five

independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and

“the four AVDD pins.”

•In Table 62, updated note 1 to say the following: “For temperature range = C, processor frequency

is limited to 400 with a platform frequency of 266.”

4/2007

• In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and

added USB to the seventh row.

•In Section 21.7, “Pull-Up Resistor Requirements,“ deleted last two paragraphs and after first

paragraph, added a new paragraph.

• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”

3/2007

• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.

• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to tCISKEW

and deleted original note 3; renumbered the remaining notes.

• In Figure 38, “JTAG Interface Connection,” updated with new figure.

• In Section 23, “Ordering Information,” replaced first paragraph and added a note.

• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.

12/2006

Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified Tddkhds for 333 MHz

from 900 ps to 775 ps.

MPC8343CVRADDB 数据表(PDF) 77 Page - Freescale Semiconductor, Inc

MPC8343CVRADDB 数据表(HTML) 77 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载