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MPC8343CVRADDB 数据表(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8343CVRADDB 数据表(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 79 page  MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 65 Clocking 19.3 Suggested PLL Configurations Table 58 shows suggested PLL configurations for 33 and 66 MHz input clocks, when CFG_CLKIN_DIV is low at reset. 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8 1 Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. Table 58. Suggested PLL Configurations Ref No.1 RCWL 266 MHz Device 333 MHz Device 400 MHz Device SPMF CORE PLL Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) 33 MHz CLKIN/PCI_CLK Options 343 0011 1000011 33 100 150 33 100 150 33 100 150 324 0011 0100100 33 100 200 33 100 200 33 100 200 423 0100 0100011 33 133 200 33 133 200 33 133 200 622 0110 0100010 33 200 200 33 200 200 33 200 200 523 0101 0100011 33 166 250 33 166 250 33 166 250 424 0100 0100100 33 133 266 33 133 266 33 133 266 822 1000 0100010 33 266 266 33 266 266 33 266 266 Table 57. e300 Core PLL Configuration (continued) RCWL[COREPLL] core_clk : csb_clk Ratio VCO Divider1 0–1 2–5 6 |
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