MPC8343VRADDB datasheet(3/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable

— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports

— Full error checking and correction (ECC) support

— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep-mode support for SDRAM self refresh

— Auto refresh

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

•

Dual three-speed (10/100/1000) Ethernet controllers (TSECs)

— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,

802.3ac™ standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 RGMII, IEEE Std. 802.3z RTBI, full-duplex

– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100

programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module

— MII management interface for control and status

— Programmable CRC generation and checking

•

PCI interface

— Designed to comply with PCI Specification Revision 2.3

— Data bus width:

–

32-bit data PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— PCI host bridge capabilities

— PCI agent mode on PCI interface

— PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration supporting five masters on PCI

— Accesses to all PCI address spaces

— Parity supported

— Selectable hardware-enforced coherency

MPC8343VRADDB 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

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