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MPC8343VRADDB 数据表(PDF) 66 Page - Freescale Semiconductor, Inc |
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MPC8343VRADDB 数据表(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 79 page  MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 66 Freescale Semiconductor Clocking 326 0011 0100110 — 33100 30033100 300 623 0110 0100011 — 33200 30033200 300 922 1001 0100010 — 33300 30033300 300 425 0100 0100101 — 33133 33333133 333 524 0101 0100100 — 33166 33333166 333 A22 1010 0100010 — 33333 33333333 333 723 0111 0100011 — — 33 233 350 604 0110 0000100 — — 33 200 400 624 0110 0100100 — — 33 200 400 823 1000 0100011 — — 33 266 400 66 MHz CLKIN/PCI_CLK Options 242 0010 1000010 66 133 133 66 133 133 66 133 133 322 0011 0100010 66 200 200 66 200 200 66 200 200 224 0010 0100100 66 133 266 66 133 266 66 133 266 422 0100 0100010 66 266 266 66 266 266 66 266 266 323 0011 0100011 — 66200 30066200 300 223 0010 0100101 — 66133 33366133 333 522 0101 0100010 — 66333 33366333 333 304 0011 0000100 — — 66 200 400 324 0011 0100100 — — 66 200 400 403 0100 0000011 — — 66 266 400 423 0100 0100011 — — 66 266 400 1 The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. Table 58. Suggested PLL Configurations (continued) Ref No.1 RCWL 266 MHz Device 333 MHz Device 400 MHz Device SPMF CORE PLL Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) |
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