MPC8343VRADDB datasheet(13/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

RESET Initialization

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8343EA.

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8343EA.

Table 9. RESET Pins DC Electrical Characteristics1

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

——

±5

μA

Output high voltage2

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 10. RESET Initialization Timing Specifications

Parameter

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN when the

MPC8343EA is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN

when the MPC8343EA is in PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is

in PCI host mode

4—

tCLKIN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is

in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR configuration signals with respect to negation of HRESET

0—

—

Time for the MPC8343EA to turn off POR configuration signals with respect to the

assertion of HRESET

—4

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