MPC8343VRADDB datasheet(59/79 Pages) FREESCALE

59 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Clocking

19 Clocking

Figure 36 shows the internal distribution of the clocks.

Figure 36. MPC8343EA Clock Subsystem

The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device

is configured in PCI host or PCI agent mode. When the MPC8343EA is configured as a PCI host device,

CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (

÷2) and the multiplexors for

PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether

CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select

whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to

synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,

with equal delay to all PCI agent devices in the system, to allow the MPC8343EA to function. When the

device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal

should be tied to GND.

Core PLL

System PLL

DDR

LBIU

LSYNC_IN

LSYNC_OUT

LCLK[0:2]

MCK[0:3]

core_clk

e300 Core

csb_clk to Rest

CLKIN

csb_clk

MPC8343EA

DDR

Memory

Local Bus

PCI_CLK_OUT[0:4]

PCI_SYNC_OUT

PCI_CLK/

Clock

Unit

of the Device

ddr_clk

lbiu_clk

CFG_CLKIN_DIV

PCI Clock

PCI_SYNC_IN

Device

Memory

Device

To Local Bus

Memory

Controller

To DDR

Memory

Controller

DLL

Clock

Div

Divider

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