MPC8572ECLPXARLD datasheet(117/140 Pages) FREESCALE

117 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

117

Package Description

25. When operating in DDR2 mode, connect Dn_MDIC[0] to ground through 18.2-

Ω (full-strength mode) or 36.4-Ω (half-strength

mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through 18.2-

Ω (full-strength mode) or 36.4-Ω

(half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect Dn_MDIC[0] to ground through 20-

(full-strength mode) or 40-

Ω (half-strength mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through 20-Ω

(full-strength mode) or 40-

Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the

DDR IOs.

26. These pins should be connected to XVDD_SRDS1.

27. These pins should be pulled to ground (XGND_SRDS1) through a 300-

Ω (±10%) resistor.

28. These pins should be left floating.

29. These pins should be pulled up to TVDD through a 2–10 K

Ω resistor.

30. These pins have other manufacturing or debug test functions. It is recommended to add both pull-up resistor pads to OVDD

and pull-down resistor pads to GND on board to support future debug testing when needed.

31. DDRCLK input is only required when the MPC8572E DDR controller is running in asynchronous mode. When the DDR

controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not

required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the

MPC8572E

PowerQUICC™ III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”,

section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding

DDR controller operation in asynchronous and synchronous modes.

32. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and

RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.

33. These pins should be pulled to ground (GND).

34. These pins are sampled at POR for General Purpose configuration use by software. Their value has no impact on the

functionality of the hardware.

Table 75. MPC8572E Pinout Listing (continued)

Signal

Signal Name

Package Pin Number

Pin Type

Power

Supply

Notes

MPC8572ECLPXARLD 数据表(PDF) 117 Page - Freescale Semiconductor, Inc

MPC8572ECLPXARLD 数据表(HTML) 117 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载