MPC8572ECLPXARLD datasheet(119/140 Pages) FREESCALE

119 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

119

Clocking

As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following

procedures can be used:

•

Start with the processor core frequency selection;

•

After the processor core frequency is determined, select the platform (CCB) frequency from the

limited options listed in Table 79 and Table 80;

•

Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from Table 78;

•

If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;

Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR

data rate to DDRCLK ratio from Table 81. Note that in asynchronous mode, the DDR data rate

must be greater than the platform (CCB) frequency. In other words, running DDR data rate lower

than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.

•

Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.

19.2

CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform

clock. The frequency of the CCB is set using the following reset signals, as shown in Table 78:

•

SYSCLK input signal

•

Binary value on LA[29:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,

because the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock

frequency is decoupled from the CCB bus frequency.

19.3

e500 Core PLL Ratio

The clock speed for each e500 core can be configured differently, determined by the values of various

signals at power up.

Table 78. CCB Clock Ratio

Binary Value of

LA[29:31] Signals

CCB:SYSCLK Ratio

000

4:1

001

5:1

010

6:1

011

8:1

100

10:1

101

12:1

110

Reserved

111

Reserved

MPC8572ECLPXARLD 数据表(PDF) 119 Page - Freescale Semiconductor, Inc

MPC8572ECLPXARLD 数据表(HTML) 119 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载