LTC4100 datasheet(23/48 Pages) LINER

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LTC1760

1760fa

OPERATION

HOST

SMB*

SMB1*

SMB2*

BAT2

BAT1

HOST, LTC1760 AND BAT1 CAN COMMUNICATE.

BAT2 ORIGINATED COMMANDS ARE IGNORED.

HOST

SMB*

SMB1*

SMB2*

BAT2

BAT1

LTC1760 AND BAT2 CAN COMMUNICATE. HOST AND

BAT1 ORIGINATED COMMANDS ARE STRETCHED IF

THE LTC1760 IS COMMUNICATING WITH BAT2.

LTC1760 AND BAT1 CAN COMMUNICATE. HOST AND

BAT2 ORIGINATED COMMANDS ARE STRETCHED IF

THE LTC1760 IS COMMUNICATING WITH BAT1.

HOST

SMB*

SMB1*

SMB2*

BAT2

BAT1

HOST, LTC1760 AND BAT2 CAN COMMUNICATE.

BAT1 ORIGINATED COMMANDS ARE IGNORED.

HOST

SMB*

SMB1*

SMB2*

BAT2

BAT1

(1b)

(1a)

(1d)

(1c)

1760 F01

*SMB INCLUDES SCL AND SDA, SMB1 INCLUDES SCL1 AND SDA1, AND SMB2 INCLUDES SCL2 AND SDA2.

LTC1760

SMBus

CONTROLLER

LTC1760

SMBus

CONTROLLER

LTC1760

SMBus

CONTROLLER

LTC1760

SMBus

CONTROLLER

Figure 1. Switch Configurations Used by the LTC1760 for Managing Dual Port Battery Communication

The dual port operation allows the SMBus Host to be

connected to the SMBus of either battery by setting the

SMB_BAT[4:1] nibble. Arbitration is handled by stretching

an SMBus start sequence when a bus collision might occur.

Whenever configurations are switched, the LTC1760 will

generate a harmless SMBus reset on SMB1 and SMB2 as

required. The four possible configurations are illustrated

in Figure 1. Sample SMBus communications are shown

in Figures 2 and 3.

2.5 LTC1760 SMBus Controller Operation

SMBus communication with the LTC1760 is handled by the

SMBus Controller, a sub-block of the SMBus Interface. Data

is clocked into the SMBus Controller block shift register

after the rising SCL edge. Data is clocked out of the SMBus

Control block shift register after the falling edge of SCL.

The LTC1760 acting as a Slave will acknowledge (ACK) each

byte of serial data. The Command byte will be NACKed if

an invalid command code is transmitted to the LTC1760.

The SMBus Controller must respond if addressed as a

combined Smart Battery System Manager at 8-bit address

×14. A valid address includes a legal Read/Write bit. The

SMBus Controller will ignore invalid data although the

data transmission with the invalid data will still be ACKed.

When the LTC1760, acting as a bus Master receives a

NACK, it will terminate the transmission and provide a

STOP condition on the bus.

Detection of a STOP condition, power on reset, or SMBus

time out will reset the Controller to an initial state at any

time.

The LTC1760 supports ARA, Write Word and Read Word

protocols as an SMBus Slave. The LTC1760 supports Read

Word protocol as an SMBus Master.

Refer to “System Management Bus Specification” for a

complete description of required operation and symbols.

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